The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). A MOS transistor includes a gate electrode as a control electrode overlying a semiconductor substrate and spaced-apart source and drain regions in the semiconductor substrate through which a current can flow. A gate insulator is disposed between the gate electrode and the semiconductor substrate to electrically isolate the gate electrode from the semiconductor substrate. A control voltage applied to the gate electrode controls the flow of current through a channel in the semiconductor substrate underlying the gate electrode between the source and drain regions. P-channel MOS transistors are formed in “pFET regions” of the semiconductor substrate and N-channel MOS transistors are formed in “nFET regions”, each of the pFET region and nFET region having an active area. The term “active area” is intended to mean part of a transistor structure through which the current is designed to flow. The semiconductor substrate may comprise shallow trench isolation (STI) regions used to electrically isolate regions of the semiconductor substrate. The trenches of the shallow trench isolation (STI) regions are filled with a deposited insulator, typically silicon dioxide.
There is a continuing trend to incorporate more and more circuitry on a single IC chip. To incorporate the increasing amount of circuitry, the size of each individual device in the circuit and the size and spacing between device elements (the feature size) must decrease. To achieve scaling of semiconductor devices, a variety of unconventional, sensitive, and/or “exotic” materials are being used. For example, high dielectric constant materials, also referred to as “high-k dielectrics”, such as hafnium dioxide (HfO2), hafnium silicon oxynitride (HfSiON), or zirconium dioxide (ZrO2) are considered for the 45 nm node technology and beyond to allow scaling of gate insulators. To prevent Fermi-level pinning, metal gates (MG) with the proper work function are used as gate electrodes on the high-K gate dielectrics, which along with the gate insulator, form gate stacks.
During fabrication of a semiconductor device, prior to gate stack formation, a silicon epitaxy may be performed on the active area of the semiconductor substrate to form an epitaxial silicon layer thereon to improve the performance of the transistors to be built, particularly high-K metal gate transistors. Such epitaxial silicon layers typically comprise a semiconductor material selected from the group consisting of silicon, silicon germanium (SiGe) and silicon carbon (SiC), or a combination thereof. Such semiconductor material is sensitive to liquid etchants such as hot phosphoric acid used to remove silicon nitride hardmasks (hereinafter “nitride hardmask”) that may be used as etch masks or selective deposition or growth masks. Removal of nitride hardmasks can damage such sensitive epitaxial silicon layers. Removal of nitride hardmasks can also damage other types of sensitive materials used in film layers.
A conventional nitride hardmask integration for patterning a SiGe epitaxial silicon layer on a pFET active area is illustrated in FIGS. 1-6. After definition of pFET and nFET active areas 16 and 18 and shallow isolation trenches 20 in a semiconductor substrate 10 as shown in FIG. 1, a nitride hardmask 22 is then deposited overlying a top surface of the semiconductor substrate 10 (FIG. 2). There may be a sacrificial oxide layer (not shown) underlying the nitride hardmask. Next, a layer of photoresist 24 is provided over the nitride hardmask and patterned as shown in FIG. 3. Next, a dry etch step is undertaken, removing the exposed portion of the nitride hardmask from the pFET region 12, with the patterned photoresist acting as an etch mask (FIG. 4), leaving the nitride hardmask portion overlying the nFET region 14. Subsequently, the photoresist is removed and oxide residues removed by wet etching using sulphuric peroxide and hydrofluoric acid (HF) (not shown). A SiGe epitaxial silicon layer 26 is then grown on the pFET active area 16 (FIG. 5). The nitride hardmask is then etched from the nFET region 14 using wet etch chemistries, such as hot phosphoric acid (FIG. 6). It is during this wet etch that the exposed epitaxial silicon layer (in this case, SiGe) will get damaged.
Typical wet etch chemistries which remove the nitride hardmask from the surface of the semiconductor substrate will also remove some of the SiGe epitaxial silicon layer, resulting in a degradation of the surface of the semiconductor substrate and a potential problem with undercutting of the SiGe epitaxial silicon layer. Exemplary SiGe loss 27 during the nitride hardmask etch is shown in FIG. 6. For example, the hot phosphoric acid used to remove the nitride hardmask from the nFET region can cause etching or pitting of the exposed SiGe epitaxial silicon layer on the pFET active area. A SiC epitaxial silicon layer is similarly susceptible to damage from hot phosphoric acid. For critical semiconductor materials such as SiGe and SiC, such damage is unacceptable. This resulting damage can degrade performance or even render a semiconductor device unusable.
In an effort to avoid such damage, a silicon oxide hardmask (hereinafter “oxide hardmask”) (not shown) rather than a nitride hardmask has been used. The oxide hardmask is typically grown on the pFET and nFET active areas of the semiconductor substrate. However, removal of the oxide hardmask itself may be problematic. The oxide hardmask is typically stripped with hydrofluoric acid (HF) which causes significant and unacceptable STI loss which can also degrade performance and render the semiconductor device unusable. The extent of STI loss with use of an oxide hardmask is typically about 15 nm for nFET active areas and 30 nm for pFET active areas.
Accordingly, it is desirable to provide methods for protecting exposed film layers including epitaxial silicon layers against damage while removing hardmasks using wet etch chemistries that would otherwise damage the film layer and cause significant STI loss. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.